module CPUTOP (
    input clk,
    // input [15:0] DI,
    input RST
    // output wire DO,A,
    // output wire R,W,H
);
    wire [15:0] Inst;
    wire [15:0] PC;
    wire [15:0] A;
    wire [15:0] DO;
    wire [15:0] DI;
    wire W,R;

sccpudataflow u_sccpudataflow(
    .clk     (clk     ),
    .RST     (RST     ),
    .Inst    (Inst    ),
    .memdataout (DO ),
    .PC      (PC      ),
    .memdatain    (DI      ),
    .alu_out (A ),
    .wmem    (W    ),
    .rmem    (R    )
);
Mem u_Mem(
    .clk  (clk  ),
    .W    (W    ),
    .R    (R    ),
    .DI   (DI   ),
    .A    (A    ),
    .DO   (DO   ),
    .PC   (PC   ),
    .Inst (Inst )
);

    
endmodule